Electrically programmable polysilicon fuse with multiple level resistance and programming

ABSTRACT

A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to an on-chip fuse device, and, more particularly,to an electrically programmable, polysilicon fuse with multiple levelresistance.

(2) Description of the Prior Art

In the art of integrated circuits, many methods are used to providemanufacturing flexibility. Of particular importance are techniques thatallow a common circuit design to be easily configured to specificapplications or to parametric requirements with little or no effect onthe manufacturing process. An example of a configuration method is theuse of on-chip programmable fuses. A fuse is a conductive element thatcan be made into an open circuit. When the element is a conductor, thecircuit operates according to a first configuration. When the element isopen circuit, the circuit operates according to a second configuration.A typical prior art, on-chip fuse is simply a metal line. A metal linecan be made an open circuit by cutting through the line using a laser.This type of fuse can be very useful. However, it requires a lasercutting source that is external to the circuit.

An alternative method to form a programmable fuse is a polysilicon line.A polysilicon line can be made an open circuit, or blown, by conductinga current through the polysilicon line that exceeds the current densitycapability of the material. Programmable polysilicon fuses such as thisare found in the art. These fuses have a limitation, however, of onlybeing binary devices. The fuses either are a conductive line or are anopen circuit. These states may be thought of as a ‘0’ state or a ‘1’state. It is highly advantageous to form a programmable fuse device thatis capable of multiple states.

Several prior art inventions relate to on-chip fuses. U.S. Pat. No.6,356,496 B1 to Carroll et al describes a method to form polysiliconresistors. The resistors are fuses that can be blown to adjust thevalue. U.S. Pat. No. 6,242,790 B1 to Tsui et al describes a method toform a variable resistance based on polysilicon resistor/fuses. U.S.Pat. No. 6,175,261 B1 to Sundaraman et al discloses an on-chip fusecircuit.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide an effectiveand very manufacturable integrated circuit device.

A further object of the present invention is to provide a method to forma programmable polysilicon fuse device capable of multiple states.

A yet further object of the present invention is to provide a method toform a programmable polysilicon fuse device with minimal impact on aCMOS process.

A yet further object of the present invention is to provide a method toform a programmable polysilicon fuse device where the state of thedevice depends on the parallel combination of polysilicon resistors.

A yet further object of the present invention is to provide a method toform a programmable polysilicon fuse device where the device is capableof performing in more than two states depending on how many resistorsare open circuited.

A yet further object of the present invention is to provide a method toform a programmable polysilicon fuse device where the relativeresistance of any resistor is controlled by the selective formation ofmetal silicide.

A yet further object of the present invention is to provide a method toform a programmable polysilicon fuse device where the relativeresistance of any resistor is controlled by the selective doping of theresistor.

Another further object of the present invention is to provide a methodto program the programmable polysilicon fuse device using on-chipcurrent sources.

A yet further object of the present invention is to provide a method toprogram the programmable polysilicon fuse device that is capable ofprogramming to more than two states using multiple pulses of current.

In accordance with the objects of this invention, a method to form aprogrammable resistor device in an integrated circuit device isachieved. The method comprises depositing a semiconductor layeroverlying a substrate. The semiconductor layer is patterned to form aplurality of lines. The lines are electrically parallel between a firstterminal and a second terminal. Any of the lines may be blown open by acurrent forced from the first terminal to the second terminal. Ametal-semiconductor alloy is selectively formed overlying a first groupof the lines but not overlying a second group of the lines.

Also in accordance with the objects of this invention, a programmableresistor device in an integrated circuit device is achieved. The devicecomprises a plurality of lines comprising a semiconductor layeroverlying a substrate. The lines are electrically parallel between afirst terminal and a second terminal. Any of the lines may be blown openby a current forced from the first terminal to the second terminal. Ametal-semiconductor alloy overlies a first group of the lines but doesnot overlie a second group of the lines.

Also in accordance with the objects of this invention, a method toprogram a programmable resistor device is achieved. The device comprisesa plurality of lines comprising a semiconductor layer overlying asubstrate. The lines are electrically parallel between a first terminaland a second terminal. Any of the lines may be blown open by a currentforced from the first terminal to the second terminal. Ametal-semiconductor alloy overlies a first group of the lines but doesnot overlie a second group of the lines. The device comprises a firstresistance between the first and second terminals. The method comprisesforcing a programming current from the first terminal to the secondterminal. The programming current causes a first line in the first groupto blow such that the device comprises a second resistance between thefirst and second terminals. The programming current is then removed.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIG. 1 illustrates a preferred embodiment of the present inventionshowing a top view of a programmable resistor device.

FIGS. 2 through 6 illustrate a preferred embodiment of the presentinvention showing a method to form a programmable resistor device.

FIGS. 7 and 8 illustrate a preferred embodiment of the present inventionshowing a method to program the programmable resistor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention disclose a method toform a programmable fuse device. The device is described herein. Amethod to program the device into more than two states is disclosed. Itshould be clear to those experienced in the art that the presentinvention can be applied and extended without deviating from the scopeof the present invention.

Referring now to FIG. 1, a preferred embodiment of the present inventionis illustrated. Several important features of the present invention areshown and discussed below. A top view of a programmable fuse device isshown. The device comprises a plurality of lines R1 18 a, R2 18 b, R3 18c, and R4 18 d comprising a semiconductor layer 18 overlying asubstrate. As an important feature, the lines 18 a, 18 b, 18 c, and 18 dare electrically parallel between a first terminal TERMINAL A and asecond terminal TERMINAL B. Any of the lines 18 a, 18 b, 18 c, and 18 dmay be blown open by a current forced from TERMINAL A to TERMINAL B.

As another important feature, a metal-semiconductor alloy overlies afirst group of the lines, such as R1 18 a, but not does not overlie asecond group of the lines, such as R2 18 b, R3 18 c, and R4 18 d. Themetal-semiconductor alloy is selectively formed overlying the firstgroup R1 18 a but not the second group R2 18 b, R3 18 c, and R4 18 dthrough the use of a metal-semiconductor mask 30 as will be furtherdescribed below. By selectively forming a metal-semiconductor alloy overpart of the lines, significantly different resistance values can becreated. For example, if the metal-semiconductor alloy is formedoverlying the R1 18 a line, as shown, then this line will exhibit a verylow resistivity value. Even though the line R1 18 a is the most narrowline, the selective inclusion of the metal-semiconductor alloy makes theR1 18 a line the lowest value resistor. The resulting thin cross sectionof R1 18 a, coupled with the low resistance value due to themetal-semiconductor alloy, causes the R1 18 a line to be blown firstwhen the device is subjected to a current pulse exceeding the minimumprogramming value as will be described below.

As another important feature, some of the lines, in this case R1 18 a,R2 18 b, and R3 18 c, are doped while other lines, in this case R4 18,are undoped. The selective doping or non-doping of lines also createslarge differences in the resistivity of the lines. Undoped lines R4 18 dwill have much larger resistivity values than doped lines R1 18 a, R2 18b, and R3 18 c. The selective doping allows significantly differingresistor values to be generated. As another important feature, thewidths of the lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d can be madedifferent for each line. This also allows different resistor values tobe generated.

Referring now to FIGS. 2-6, the programmable fuse device is illustratedin cross section. Several important features of the present inventionare shown and discussed. In particular, the key features of a preferredmethod of formation of the present invention are described. Referringagain to FIG. 2, as a first preferred feature, a substrate 10 isprovided. The substrate 10 may comprise any semiconductor material ormay comprise a semiconductor on insulator (SOI) material. Preferably,the substrate 10 comprises silicon. An insulating layer 14 is shownformed overlying the substrate 10. This insulating layer 14 is shown asa shallow trench isolation 14. Alternatively, local field oxidation(LOCOS) could be used to create a non-active area.

As an important feature, a semiconductor layer 18 is formed overlyingthe substrate 10 and, preferably, overlying the insulating layer 14.Known semiconductor materials may be used to form the semiconductorlayer 18. However, it is preferred that the semiconductor layer 18comprises silicon and, more preferred, that the layer 18 comprisespolysilicon. For example, a polysilicon layer 18 of between about 500 Åand about 2,500 Å is formed overlying the insulator layer 14. In themost preferred case, the polysilicon layer 18 comprises the samepolysilicon layer used in the formation of transistor gates for CMOSdevices on the integrated circuit device. In this way, the method offormation of the present invention can be performed with minimal changesto the standard production process. The polysilicon layer 18 may bedeposited, for example, using a chemical vapor deposition (CVD) process.

The semiconductor layer 18 may be formed as an intrinsic layer or as adoped layer. If intrinsic, then the semiconductor layer 18 has a verylow, dopant ion concentration. If doped, then the dopant ion, such asphosphorous, boron, or arsenic, concentration is sufficiently high tocause the semiconductor layer 18 to be described as n-type or p-type. Ifa polysilicon layer 18 is used, then this film may be depositedintrinsically or deposited with in situ doping. Alternatively, thepolysilicon may be conformally doped after deposition to a desiredstarting concentration.

Referring now to FIG. 3, the semiconductor layer 18 is patterned to forma plurality of lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d. Thepatterning may be performed using any of the known methods. For example,a photosensitive film, not shown, may be deposited overlying thesemiconductor layer 18. The film is exposed to actinic light through amask and then developed. The photosensitive film will expose thesemiconductor layer 18 according to the pattern of the mask. The exposedsemiconductor layer 18 is then etched away using the film as an on-chipmask. The photosensitive film is then stripped away. The resulting linesR1 18 a, R2 18 b, R3 18 c, and R4 18 d can be made the same width. Morepreferably, each line is made to a width that corresponds to the desiredrelative resistance of that line. The most resistive lines are made thethinnest. Likewise, by making a line wider, such as in the case of R4 18d, that line can carry a large current density without being blown open.This feature can be optimal used to tailor the order that the lines willblow. In the example, four lines R1 18 a, R2 18 b, R3 18 c, and R4 18 dare formed. In practice, the device comprises two or more lines.

Referring now to FIG. 4, another important feature of the presentinvention is illustrated. As described above, the lines R1 18 a, R2 18b, R3 18 c, and R4 18 d may be selectively doped to create optimalresistivity values for the lines. In this exemplary case, ions areimplanted 26 into lines R1 18 a, R2 18 b, and R3 18 c to reduce theresistivity of these lines. A doping mask 22 is defined such that itcovers the R4 18 d line and prevents the ion implantation 26 into thatline 18 d. In this way, the doped group of lines R1 18 a, R2 18 b, andR3 18 c have a lower resistivity than the non-doped group of lines R4 18d.

Referring now to FIG. 5, an important feature of the present inventionis illustrated. A second masking layer 30 is formed exposing a firstgroup of lines while covering a second group of lines. As shown, thefirst group of lines comprises line R1 18 a and the second group oflines comprises lines R2 18 b, R3 18 c, and R4 18 d. The second maskinglayer 30 preferably comprises a photosensitive or photoresist layer andmay be patterned as described above. A metal layer 34 is then formedoverlying the second masking layer 30 and the exposed lines R1 18 a. Themetal layer 34 preferably comprises a metal that will react with thesemiconductor layer 18 to form a metal-semiconductor alloy. If thesemiconductor layer 18 comprises silicon or polysilicon, as ispreferred, then it is also preferred that the metal layer 34 comprisescobalt, titanium, nickle, or platinum. The metal layer 34 may be formedby physical or chemical vapor deposition to a thickness of between about10 Å and about 300 Å.

Next, the metal layer 34 and the semiconductor layer 18 are annealed tocatalyze the formation of metal-semiconductor alloy on the exposed lineR1 18 a. For example, the integrated circuit device may be heated to atemperature of between about 300° C. and about 800° C. Referring now toFIG. 6, a metal-semiconductor alloy layer 38 is formed only on theexposed line R1 18 a. In the preferred case, where the semiconductorlayer 18 is silicon or polysilicon, the metal-semiconductor alloy layer38 comprises a metal silicide material such as TiSi₂, CoSi₂, NiSi, orPtSi_(x). The metal-semiconductor alloy layer 38 is preferably formed toa thickness of between about 10 Å and about 300 Å. Following the annealstep, the unreacted metal layer 34 is removed.

Referring again to FIG. 1, the resulting programmable fuse device isagain shown in top view. As noted in the preferred embodiment of themethod of formation, the lines R1 18 a, R2 18 b, R3 18 c, and R4 18 dare formed such that R1 18 a is the only line with themetal-semiconductor alloy, such that lines R1 18 a, R2 18 b, and R3 18 care doped, and such that line R4 18 d is neither doped nor features themetal-semiconductor alloy.

In the beginning state, the resistance of the device comprises theparallel combination of the resistance of lines R1-R4. This is the firstresistance of the device and represents the first stored state of thedevice. Note that the first state, where all the lines are connected,represents the smallest resistance of the device.

Referring now to FIG. 7, a first programming of the device is nowperformed. A first programming current I_(PROGRM1) is forced through thedevice from TERMINAL A to TERMINAL B. The first programming currentI_(PROGRM1) is large enough to cause the weakest line in the device tobe blown open. In this case, the weakest line is R1 18 a. R1 18 a is theweakest line for several reasons. First, the inclusion of themetal-semiconductor alloy greatly reduces the resistivity of the line.Second, line R1 is doped. Third, line R1 is the thinnest line. As aresult, most of the programming current is conducted in the R1 line.When the thermal capability of the metal-semiconductor alloy layer isexceeded, this layer is blown open. At this point, the excessive currentis immediately conducted in the bulk of line R1 and rapidly exceeds thethermal limit of the semiconductor layer. Therefore, line R1 is blownopen as shown. The first programming current I_(PROGRM1) is designed tobe a brief pulse that is large enough in value to blow the weakest lineR1 without damaging the other lines R2-R4.

As a result of the first programming pulse, the device is programmed tothe second state. In the second state, the weakest line R1 is blown openwhile the remaining lines R2-R4 are left connected. As a result, thedevice resistance is transformed to a higher value due to the absence ofR1. This second resistance value corresponds to the second state of theprogrammable resistor device.

Referring now to FIG. 8, the programming method is repeated to programthe device from the second state to the third state. A secondprogramming current I_(PROGRM2) is force through the device fromTERMINAL A to TERMINAL B. The current I_(PROGRAM2) and duration issufficient to blow open the next weakest line R2. In this case, line R2is a doped line. Since this line is the thinnest remaining line, thethermal ability is the least. After the R2 line is blown, the deviceenters the third state. The third state corresponds to a thirdresistance that is the parallel combination of R3 and R4. The sequencemay be repeated yet a third time to blow open the R3 line 18 c and toprogram the device to the fourth state where the resistance of thedevice is merely R4.

It can be seen how the unique combination of features of the presentinvention creates an advantageous device. The device uses a parallelcombination of a plurality of lines, the selective formation of ametal-semiconductor alloy on a first group of lines but not a secondgroup of lines, and the selective doping of some lines yet not otherlines. The resulting device is particularly useful as a programmable, ortrimmable, resistance value for analog circuits. It can be used incombination with built-in self-test (BIST) or built-in self-repair(BISR) circuits. The fuse is scaleable with the prevailing technology ofthe integrated circuit device. Multiple logical levels may be programmedby repeating the programming pulse. The polysilicon fuse structure ofthe present invention consists of strips with combinations of N, P, orintrinsic dopant regions and/or silicide or non-silicide regions. Thisis a unique structure that differs substantially from variable resistorstructures formed using variable length or width polysilicon strips.

The resulting programmable resistor device may be applied advantageouslyto the formation of a chip identifier for an integrated circuit device.A single such programmable resistor, or a combination of suchprogrammable resistors, may be used to form a unique identifier for anintegrated circuit device.

The advantages of the present invention may now be summarized. Aneffective and very manufacturable integrated circuit device is achieved.A method to form a programmable polysilicon fuse device capable ofmultiple states is achieved. The method of formation has minimal impacton a standard CMOS process. The method allows the state of the device todepend on the parallel combination of polysilicon resistors. The methodallows the device to be capable of performing in more than two statesdepending on how many resistors are blown open. The method allowsutilizes relative resistance of the resistor lines controlled by theselective formation of metal silicide. The method utilizes the relativeresistance of the resistor lines controlled by the selective doping ofthe resistor. A method to program the programmable polysilicon fusedevice using on-chip current sources is achieved. The method to programthe programmable polysilicon fuse device is capable of programming tomore than two states using multiple pulses of current.

As shown in the preferred embodiments, the novel methods and device ofthe present invention provide an effective and manufacturablealternative to the prior art.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. A method to form a programmable resistor device in an integratedcircuit device comprising: forming a semiconductor layer overlying asubstrate; patterning said semiconductor layer to form a plurality oflines wherein said lines are electrically parallel between a firstterminal and a second terminal and wherein any of said lines may beblown open by a current forced from said first terminal to said secondterminal; and selectively forming a metal-semiconductor alloy overlyinga first group of said lines but not overlying a second group of saidlines.
 2. The method according to claim 1 wherein said semiconductorlayer comprises silicon.
 3. The method according to claim 1 wherein saidsemiconductor layer comprises polysilicon.
 4. The method according toclaim 1 wherein said programmable resistor device is a chip identifierfor said integrated circuit device.
 5. The method according to claim 1wherein said metal-semiconductor alloy comprises metal silicide.
 6. Themethod according to claim 1 wherein said step of selectively forming ametal-semiconductor alloy comprises: forming a masking layer overlyingsaid plurality of lines wherein said masking layer covers said secondgroup of lines but exposes said first group of lines; depositing a metallayer overlying said masking layer and said plurality of lines whereinsaid metal layer contacts said first group of lines; annealing saidmetal layer to form said metal semiconductor alloy overlying said firstgroup of lines; and removing unreacted said metal layer.
 7. The methodaccording to claim 1 further comprising selectively doping saidplurality of lines prior to said step of selectively forming ametal-semiconductor alloy.
 8. The method according to claim 5 whereinsaid first group of lines is doped and said second group of lines is notdoped.
 9. The method according to claim 1 wherein said first groupcomprises a single line, wherein said second group comprises more thanone line, and wherein said single line comprises a smallest resistanceof all of said lines.
 10. A programmable resistor device in anintegrated circuit device comprising: a plurality of lines comprising asemiconductor layer overlying a substrate wherein said lines areelectrically parallel between a first terminal and a second terminal andwherein any of said lines may be blown open by a current forced fromsaid first terminal to said second terminal; and a metal-semiconductoralloy overlying a first group of said lines but not overlying a secondgroup of said lines.
 11. The device according to claim 10 wherein saidsemiconductor layer comprises silicon.
 12. The device according to claim10 wherein said semiconductor layer comprises polysilicon.
 13. Thedevice according to claim 10 wherein said programmable resistor deviceis a chip identifier for said integrated circuit device.
 14. The deviceaccording to claim 10 wherein said metal-semiconductor alloy comprisesmetal silicide.
 15. The device according to claim 10 wherein saidplurality of lines is doped.
 16. The device according to claim 10wherein said first group of lines is doped and said second group oflines is not doped.
 17. The device according to claim 10 wherein saidfirst group comprises a single line, wherein said second group comprisesmore than one line, and wherein said single line comprises a smallestresistance of all of said lines.
 18. A method to program a programmableresistor device wherein said device comprises: a plurality of linescomprising a semiconductor layer overlying a substrate wherein saidlines are electrically parallel between a first terminal and a secondterminal and wherein any of said lines may be blown open by a currentforced from said first terminal to said second terminal; and ametal-semiconductor alloy overlying a first group of said lines but notoverlying a second group of said lines wherein said device comprises afirst resistance between said first and second terminals; and whereinsaid method comprises: forcing a programming current from said firstterminal to said second terminal wherein said programming current causesa first line in said first group to blow such that said device comprisesa second resistance between said first and second terminals; andremoving said programming current.
 19. The method according to claim 18wherein said semiconductor layer comprises silicon.
 20. The methodaccording to claim 18 wherein said programmable resistor device is achip identifier for said integrated circuit device.
 21. The methodaccording to claim 18 wherein said metal-semiconductor alloy comprisesmetal silicide.
 22. The method according to claim 18 wherein saidplurality of lines is doped.
 23. The method according to claim 22wherein said first group of lines is doped and said second group oflines is not doped.
 24. The method according to claim 18 wherein saidfirst group comprises a single line, wherein said second group comprisesmore than one line, and wherein said single line comprises a smallestresistance of all of said lines.
 25. The method according to claim 18further comprising: forcing a second programming current from said firstterminal to said second terminal wherein said second programming currentcauses one of said lines in said second group to blow such that saiddevice comprises a third resistance between said first and secondterminals; and removing said second programming current.